Dynamic pulse gating transistor circuitry



4 shets-sheet 1 S. SCHOEN ETAL DYNAMIC PULSE GATING TRANSISTOR CIRCUITRY Feb. 10, 1959 Filed Feb. 4, 1955 Feb. 10, 1959 v s. scHoEN ET AL 2,873,384

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United States arent()n DYNAMIC PULSE GTING TRANSISTOR CR'CUITRY `Seymour Schoen and Charles A. Krause, Los Angeles,

Calif., as'signors to The National Cash Register Company, Dayton, Ohio, a corporation of Maryland Application February 4, 195s, Serin No. 436,156

11 claims. (ci. sin-sam This invention relates to pulse `gating circuits and 4more particularly to a bistable state circuit arrangement utilizingtra'nsistor components.

It has been (previously shown in the electronic art that digital computing systems can be designed bythe use of a memory device in combination with a logical interconnection of a plurality of basic bistable state circuits In such designs pair of trigger inputs and a pair of outputs. In has further been shown that if Vall these basic bistable state circuits are available in a standardized package arrange` ment, the problem of designing a particular computer 'system can be highly simplitiedinasmuch as thecircuit networks jfor interconnecting the outputs of the `bistable `s'tate'crcuits to the trigger inputs thereof can/*be delined `'by logical equations using the notation of Boolean algebra.

Such bistable state circuits have been designed in the past with the use of electron tubes, but inasmuch `as transistor components dissipate, by far, less power than electron tubes and operate well in conjunction with crystaldiode circuits since they themselves are crystal devices, la'bistable state circuit utilizing transistor components particularly lends itself for use in such a stand- It is, accordingly, an object of this invention to provide a `basic transistor computer circuit, having standardized `output and inputarrangements, whereby `a plurality lor these circuits can Vbe interconnected by logical networks so as to `function as a desired electronic computing system. y l p It is a further object of this invention to provide a 'novel bistable state transistor circuit arrangement which selectively generated by applying trigger signals to a true or false input thereof.

Bistable state circuits have `been previously designed to operate in accordance with 'the non-return-toizero digital techniques, that is, all changescalledfor in`the lbistable state circuits of a particular logical system are "made precisely at the `same instant, i. e., at the'end of abasic timing `signal period, and a change in state or a bistablestate circuit-is made only when a change in `its output signal isrequired. Thus theo'utput signals of-a 'bistable state circuit are maintained in a `particular state indefinitely, until the circuit istriggered at the `.endf'of a timing signal rperiod. `This `mode ofoperation i has well-known inherent timing and logical advantages, -but asrssi ice causes difiiculty when high frequency operation is desired and a large amount of power is needed to drive the logical networks.

. Bistable state circuits have also been designed to operate in accordance with the return-to-zero digital techniques. These latter circuits, known as dynamic flipflopsf are advantageous in that they permit high frequency operation and enable A.C. coupled drivers `to be employed, thus producing more available `power for driving the logical networks. In addition, these latter circuits provide a lower output impedance for the charging ofstray capacitance.` However, these latter circuits present difticult` timing problems inasmuch as they must have a known delay inserted between their input and youtput circuits in the form of a delay line .or similar device.

"TheQtiming of the signals required to gate `the outputs of thesedynamic ip-ilops to the inputs thereof is then `afunction not only of these artilicial delay lines, but also of the inherent ampliiier delays. To operate these dynamic tlip-,l'lops, it `has thus usually been necessary to generate threeA or more timing signal sources varying in *phase'lrelationand, furthermore, to closely control the "width of 'the waveforms" of these timing signals.

The `bistable state circuit of the present invention may be ,considered to be a hybrid combination of the above described ycircuits in that a single leg transistor iiip-op circuitis provided which operates in the non-return- "to-'zerof system, i. e., it maintains an output signal in a particular `state uindeinit'ely, changing only when the hip-dop c'irciiitis triggeredl vat the end of a `timing signal period. However, the output signals ot the bistable state lcircuitfin thepresent invention are manifested as a `series oi "discretepulses typical of the "freturn-to-zero systems.

Thus in the circuits of the present invention, lsingle leg flip-flop is triggered `by the fall of a clockpulse A'applied on its input, and its output serves to gate the subsequent clock` pulses derived from the `same timing source `onto `the output gates, thus `automatically providing a delay of one clocktpnul'se period without the use of any ,external delaydevices.` This scheme not only eliminates thelneed of delayfdevices but Lalso ensures that the delay will `be `exactly ionefclockpulse period, thereby precisely controllingithe timing `of all clock pulses `appearing on the outputs,

It Ais thuslanotherobject of this invention tto provide a bistable state circuit arrangement which. .combines `the inherent `timing and logical advantages of the 5nonreturn-to-zero digitaltechniques with the higher frequency and llarger power coupling advantages of the "ireturnto-zero digital techniques. `Briefly, the invention herein disclosed comprises a 'point-contact type (PNP) transistor operating asa :flipop -circuit capable ofibeing `triggered intoone state or `theotherby trigger signals applied to the emitterorbase thereof, respectively, `via appropriate respective ditfer- :entiating and clipper circuits. The signalonthe collector fof vthisilip-op `transistor is conveyed to `the baseiof :a

gating transistorwhichbhas a .timing signal, int-he form Iota `square wave, applied to its emitter and haslitscollector electrode output .connected to azprimary 'winding `cfa transformer. A `pairot output gates :are provided for gating signals `from Isaid timing signal source onto a pair-of output leads. The :controlinputs to thesesgates are normally Abiased such thatone gate is open and the other is closed.` Signals generated on two :oppositely `wound secondary'windingsof thetransformer are respectively applied `to the` control inputs of each of these two output gates, toithereby reverse `theirnormaloperating status, tthereby gating timing signals fromthe .timing signal source through the-opposite outputgate.

.Tshustthe output, in the `form ofcsquare wave rpulses, as obtained 4frornreither oneror` the other Iruff thes'eigates Patented Feb. 10, 1959 nected by way of collector 26 to the 3 is governed by the application of trigger signals to one or the other of the two inputs of the flip-flop transistor.

The foregoing objects, aspects, features, and advantages of the invention as well as a more complete understanding thereof may be obtained by referring Ato the ensuing detailed description of the drawings in which:

Fig. 1 is a schematic diagram of the invention. Fig.'2 is a graph of typical waveforms useful in explaining the operation of the invention.'

Fig. 3 is an emitter current versus emitter4 voltage graph, useful in explaining the operation of the transistor flip-flop circuit shown in Fig. 1.

Fig. 4 is a block diagram of a frequency dividing circuit devised from a combination of two basic circuits presented in Fig. 1.

Fig. 5 is a graph of typical waveforms useful in ex-4 plaining the operation of the frequency dividing circuit Lof Fig. 4.

Referring to the schematic diagram of Fig. 1, the preferred embodiment of the present invention will now be broadly described. The circuit includes a ilip-op circuit arrangement 12 comprised of a transistor T1 having a collector 13 which can have either a high or -a low level signal thereon. If transistor T1 is triggered by a signal on trigger input 8, which is connected by way of differentiator and clipper circuit to the emitter input junction 7, the signal on collector 13 is low. On the other hand, if transistor T1 is triggered by a signal on trigger input 9, which is connected by way of differentiator and clipper circuit 11 to the base input junction 7a, the signalv on collector 13 is high. The collector 13 of transistor T1 is connected to the base 17 of a transistor T2 arranged to function as gate 16.- A timing signal source 24 supplies emitter 25 of gate transistor T2 with clock signals C, which pulses are conprimary winding 27 of transformer 2S when base 17 is at a low potential, i. e., when gate 16 is effectively open. Output lines 29 and 30 taken from the two oppositely wound secondary windings 31 and 32 of transformer 28 convey signals to input diodes 67 and 71 of the diode gates 35 and 36, respectively. Aline 41 from timing signal source 24 supplies clock signals C to the other input diodes 68 and 72 of gates 35 and 36, respectively. As will be -described hereinafter, gates 35 and 36 function to gate `clock signals C from timing signal source 24 onto either output lead 33 or onto output lead 34 depending on whether flip-flop transistor T1 is triggered by a signal on trigger input 9 or trigger input 8.

It should be understoodA that the` transistor flip-dop 12 operates in the non-return-to-zero system. In such systems the signal on the collector output remains at a low or high voltage operating level for the duration of theseveral timing signal periods that the binary information does not change. On the other hand, the gated output information is represented in the return-tozero system, i. e., binary information is represented on the Y output leads 33 and 34 by signals which return from a high to a low voltage operating level during each timing signal period. Thus in the preferred embodiment of the invention, for the duration of the timing signal periods that the ip-flop transistor T1 is in itshigh or low conductingstate, binary information signals appear as discrete pulses during each timing. signal period on one of the output leads 33 or 34; while the other output lead is maintained at the low voltage operating level.

Referring to the circuitry of Fig. l in greater detail,

di'erentiator and clipper circuit 10 includes capacitor 4 which, together with grounded resistor 5, serves to differentiate square wave pulses applied to input 8. A diode 6 then serves to pass only the negative portion of the differentiated pulse to emitter junction 7 of an inl put circuit connected to the emitter of transistor T1. A

dierentiator and clipper circuit 11 is similarly arranged :.to enable only 4negative portions of differentiated pulses 4 derived from square wave pulses applied on input 9 to be sensed on base junction 7a of transistor T1.

Transistor T1, which is of the point-contact type, has the base thereof grounded by way of inductor 18 and a diode 19. The emitter input circuit includes a 45 volt clamping battery 23, the negative end of which is connected to ground and the positive end of which is connected to junction 7 by way of resistor 37. Junction 7 is further connected to ground by way of diode 21 and the negative terminal of a 3 volt bias battery 22.

The collector 13 of flip-flop transistor T1 is connected by way of load resistor 20 to the -45 volt potential of The collector 13 from flip-dop transistor T1 is connected to the base 17 of transistor T2 which is grounded by resistor 40. The emitter 25 of `transistor T2 is connected by way of resistors 45 and 47 to the negative terminal of a 22 volt battery 46, the positive terminal of which is grounded. Signals applied `on terminal' 48 vof timing signal source 24 are sensed on the emitter 25 of gating transistor T2 by way of coupling capacitor 49 connected t0 the junction of resistors 45 and 47. The collector 26 from gating transistor T2 is connected to one end of primary winding 27 of transformer 28. Transformer 28 has the other end of its primary winding 27 connected to a -45 v. D. C. bias voltage by way of limiting resistor 51, shunted `by by-pass capacitor 52. Transformer 28` has a secondary winding 32 which is wound in the same sense as primary winding 27, and a secondary winding 31 which is wound in the opposite sense of primary winding 27. Secondary winding 31 is connected to a circuit loop comprised of diode 53 in series with the parallel combination of diode 54 and resistor 55. This loop is connected to a bias voltage of -16 volts supplied by battery 58. Secondary winding 32 is similarly connected to a circuit loop comprised of diode 60 in series with the parallel combination yof diode 61 and resistor 62. This loop is connected to a bias voltage of -22 volts supplied by battery 64. Y

Secondary windings 31 and 32 are connected to diode gates 35 and 36, respectively. Output line 29 connects winding 31 to the cathode of diode 67 of gate 35; and output line 30 connects winding 32 .to the cathode of diode 71. A line 41 is connected t-o the cathode of diode '68 of gate 35, and the cathode of diode 72 of gate 36.

This line 41 is coupled by wayof capacitor 74 to termiclamping diode 74a shunted by resistor 73. In gate 35, the anodes of diodes 67 and 68 are connected to junction 69 which is connected, in turn, to ground by way of a load resistor 70. Gate 36 is similarly arranged with its load resistor 66 returned to ground.

The operation of flip-flop transistor T1 is based upon the negative resistance characteristics of the point-contact type transistor. This inherent property of the point-contact type transistor will be better understood by reference to Fig; 3, showing a graph `of emitter voltage VE versus emitter current IE for a grounded base circuit configuration. This impedance curve Z can be divided into three regions. Region EH, called cutoff, indicates but a small emitter current excursion for a rather large emitter voltage change. This region EH of the impedance curve Z represents a positive resistance characteristic of the circuit.` In region HI, the negative resistance region, the

kregion is commonly referred to as saturati-on.

In accordance with the magnitude of certain components, a load line can be drawn to intersect curve Z. Il: is to be noted that the prior art teaches that if the emitter circuit load line intersects the dynamic current-voltage highbackresistance of diode 21.

.generative feedback. `negativeiltesistance slope .in region H1 of the impedance curve `Z in Fig. 3. .isfefiected and, as a result, even a greater amount of interesser;

The slope of the load line can be changed by altering the magnitude of the resistorswhich determine it. In -the .inventive combination herein disclosed, this load line `switching operation is conveniently `combined with circuit `triggering as will next be explained.

Flip-nop transistor T1 has .two stable current states, i. e., the current on collector output 13 can be high or low (see Fig. 2). The circuit can 'be triggered from one stable state to the other by the application of an appropriate pulse to the emitter 14 or to the base 15 thereof.

For purposes of explanation, assume that the collector 13 of flip-flop transistor T1 (Fig. l) is initially in a relattively low current state. Under this condition, transistor T1 is effectively nonconductive, i. e., the emitter 14 is now biased in a relatively large` reverse direction `with respect to the base 15. The circuit is now operating on a load line d1, the slope of which is determined largely by the forward resistance of diode 21, and the relatively high back resistance of diode 14a. The point of intersection P1 of load line d1 with impedance curve Z determines the relatively low current state. The'curve Z is` clamped at peakH (ground)` by means of the grounded diode 19 in the circuit loop which also includes battery 23 and resistor "39 therein. The voltage at junction 7 is dependent largely on negative potential supplied by lthe 3 voltbattery "22, whereas the voltage at junction 7a is practically at ground. The collector 13, which is connected lby load resistor to the negative terminal of 45 volt battery 42, is clamped at -22 volts by diode 44 and battery 43. IThis arrangement helps to provide a relatively low output impedance at the collector 13 by decreasing the loading effect of transistor T2.

`When the negative portion of the differentiated pulse is applied to junction 7a, the base potential of transistor T1 is lowered thereby; consequently the currentof emitter 14 increases and the operational point of the circuit passes over hump H into the negative resistance region H1 of the curve of Fig. 3. As the emitter current becomes greater than zero, the'biasing current therefor is exceeded by the positive base current. A current reversal now occurs in diodes 21 and 14a. As the emitter 14 becomes more negative, current now passes through the low .forward resistance of diode 14a and the relatively The circuit load line thus begins to shift. During this transition, inductor 18 Vtends to resist a change incurrent therethrough, i. e.,

acts as a high impedance. However, owing to the` normalfdirection of current in the various electrodes, lthe `resulting voltage drop vacross inductor 1-8 will be seriesaiding with the emitter voltage and hence provide re- It is 4this feedback which effects Thus `more and more emitter current current appears on collector 13 until a quiescent state iswattainedtas.determined by the point of intersection P2 of `shifted load line d2 with curve Z.

`A `relatively high current now exists on the collector 1`3 and also on load resistor 20. Diode 44, however, now presents ahighirnpedance to current therethrough.

.Itistto be 'noted that the clamp for valley point l (fig.

3) is'provided by the current loop including battery 77,

Idiode 78, inductor 18, and diode 1i).

In order to trigger the'transistor T1 flip-op-circuit "back to its low current collector state, a trigger `pulse must subsequently be applied to -emitter junction 7. The *eifectofthis pulse is to` make the emitter voltage more .lnegative, thus decreasing the emitter current and `eifecting a traverse of impedance curve Z back into cut-olf region "EHwhile the circuit operational point issimultaneously switched-from P2 Ibach to P1.

"It should Lbe noted "that diodes 119 and u*78 `aid in clamping peak I-Iy andl'valley. I, respectively, "offi'rnpedance curve Z. If these diodes -were omitted, current varia- Consider now how the collector current of llip-'liop transistor T1 is utilized to controlthe passage Aof clock pulses C through gating transistor T2. Timing signal source 24 comprises a sequential train of clock pulses C (Fig. 2) applied to coupling capacitor 49 b`y way of terminal 48. Transistor T2 has the base17 thereof connected to the collector 13 of transistor T1. 'lTheemitter 25 of transistor T2 is connected to `biasfhattery 46 by way of resistors 45 and 47 andthe'collector-Zoftransistor T2 is connected to the primary winding 27 ofttransformer 28. Transistor T2 is openf i. le.,has relatively high collector current, when the collector current of transistor T1 is low; whereas the gating transistor T2 is closed when" this currentoutput is high.

When collector current from transistor T1 is small, the base V17 of transistor T2 is at essentially the same potential (-22 v.) as the emitter 25 thereof inasmuch as battery 46 and battery 43 are of the same value. Consequently a clock pulse applied lto the emitter `25 of transistor T2 is transmitted to the primary winding 27 of transformer 28 in the`form of amplified current from the collector 26 of transistor T2.

When the current of collector 13 of transistor T1 `is large,`ho`wever, the base 17 of'transistor T2 is ata more positive potential than the emitter 2S thereof;conse quently the current path through transistor T2 is effectively blocked and no clock pulses are passed thereby to the primary winding 27 of transformer 2S.

The collector 26 of transistor T2 is `connected'toI the primary winding 27 of transformer 28, andithe `other end of this primary winding 27 is connected to a'suitable -45 volt D. C. source byway of current limiting resistor S1 which is shunted by a by-pass capacitor 52 `by clamping diode 61having a` clamp potential source 64 in `series therewith. Resistor 62 is a. load resistor. Grounded resistor 65 serves as a current path for 'gate 36 as will bediscussed next. 4

Consider now the operation of gate circuits 35 and 36. Gate circuit 35 has the cathode `equivalent end of its diode 68 normally vmaintained at the potential of battery `46 (--22 volts), while thecathode equivalent end of its diode 67 is normally'maintained at thepotential of battery 58 (te-16 volts). The difference of potentials of batteries 46 and 58 render possible the unique operation of this gate 35. When gating transistor T2 is effectively open, i. e., the collector 13 of transistor T1 has a relatively low current, a' negative pulse generated on secondary Vwinding *31 appears at the input tothe cathode equivalent end of diode 67 simultaneous `with`a clockpulse C applied to the cathode equivalent end of diode 68. Under these conditions,`no output pulse is generated on output lead 33 because the voltage at ,junction 69 of gate 3S falls to the lowest value as v-determined by the lower level of the negative pulse generated on output line `Z9 by 'secondary winding 31.

In theabsence of any negative pulse from 'secondary winding 31, i. e., when transistor T2 is feectively"c1osed, a clock pulse C is gated through gate 35 since a steady 16 volt signal Vfromtbattery -58 `isapplied tolthe cathode equivalent end ofr'diode v67 .and the'potential at `ju'ntifticjin 169 is thus enabled to 'rise fand fall in accordance with f the same potential.

put lead '33 in synchronizationwith a clock pulse C.

Gate 36 comprises the combination of diodes 71 and 72 connected to ground potential by way of resistor 66. The cathode equivalent ends of diodes 71 and 72 are connected to batteries 64 and 46, respectively, which are both of the same potential, e. g., 22 volts. Consequently an output pulse` appears on output lead 34, only when a positive pulse from secondary winding 32 and a clock pulse C are applied simultaneouslyto the cathode equivalent ends of diodes 71 and 72, respectively, because the potential at junction 79 will then rise and fall in accord- .ance with these two simultaneous input signals. This action takes place when gating transistor vT2 is effectively reopen.

The operation of the circuit of Fig. 1 will now be further claried by reference to the chart of waveforms in Fig. 2. It will be assumed that the circuit is initially operating with output pulses (hereinafter designated F 1C) appuearing on output lead 34, i. e., the collector 13 of transistor T1 is initially in a low conducting current state (gate 16 is open), as shown by the waveform designated collector (T1) in the graph of Fig. 2.

Consider first the effect of an appropriate signal applied to trigger input lead 9. In the graph of waveforms shown inFig. 2, this signal is designated ofl. The effect of this signal is to trigger flip-flop transistor T1, by virtue of the negative portion of the differentiated waveform 80, to a relatively high cuirent condition, as evidenced by the positive swing 84 of the waveform designated collector (T1) inl Fig. 2. This relatively high current on' collector (T1) is conveyed to gating transistor T2, Aeffectively closing same, and consequently cutting off the flow of clock signals C fromtming signal source 24 to the primary winding 27 of transformer 28. Under these conditions gate 35 is effectively open and, as shown in the chart, timed output signals FIC pass therethrough to output lead 33. However, since gating transistor T2 is now closed, no timed output signals FIC pass through diode gate 36 to output lead 34.

Consider next the effect of an appropriate signal f1 yapplied to trigger input lead 8. The flip-flop transistor T1 is now triggered by the negative signal 81 to a relat tively low current condition as evidenced by the negative swing 85 in the waveformdesignated collector (T1) in the graph. Gating transistor T2 is now open to clock signals C received from timing signal source 24 since the emitter 25 and the base 17 thereof are at substantially Consequently the primary winding 27 of transformer Z8 is now energized by signals designated as collector (T2) in Fig. 2. The two secondary windings 31 and 32 of transformer 28 now yield an output y signal F1 and an inverse output signal F1', respectively, as

indicated in Fig. 2. The effect of output signal F1 is to ,open gate 36 such that a clock pulse C being simultaneously received on line 41 is sensed an output lead 34 as a pulse F1C. The inverse signal F1', however, prevents a clock signal C from passing through gate 35 to output lead 33.

This output condition, i. e., a train of signals FIC appearing on output lead 34, continues until an appropriate signal f1 is subsequently again applied to input lead 9.

The negative signal 82 obtained by differentiating signal f1 `switches the circuit to the condition in which an F1Cy pulse appears on output lead 33. As shown in the graph, a signal f1, applied on input lead 9 again reverses the state of the circuit at the end of the clock pulse period. Thus it has been described how a train of output signals Y can appear on one of two output leads, depending upon which of the two input leads last received an appropriate signal.

Fig. 4 is a block diagram showing how a pair of bas1c A transistor computercircuits, designated as stages F1 and F2, can be used in combination so asv to form a frequency divider circuit for clock signals'C from'a timing source. A circuit of this type is of utility in digital computers in .such applications as pulse counters, or similar cyclical vto the bistable state circuit shown in Fig. l, like coml ponents thereof bear like numerical reference designations to those in the circuit of Fig. l with primes and double primes, respectively, affixed thereto. In this frequency divider circuit, the F lC output of circuit stage F1 is fed back by way of line 36 to the f1 trigger input thereof, while the F1() product output is fed back by way of lead 87 to the f1 trigger input thereof. In a similar manner, the F1F2C output of stage F2 is fed back by way of lead 88 to the f2 trigger input thereof, while the F1F2C output is fed back by way of lead 89 to the f2 trigger input.

Timing signal source 24 directs clock pulse signals C to gates 35' and 36 of stage F1 as well as to gate circuit 16 thereof. Timing signal source 24 also directs clock pulse signals C to gate circuit 16 of stage F2. However, the signal inputs to the gates 35 and 36 of stage F2 are derived from the output F1C of stage F1.

In ordervto gain understanding of how the basic transistor circuit previously explained in Fig. l operates in this combination as a frequency divider circuit, reference will occasionally be made to Fig. 5 which is a representadependent upon the high or low current output status of flip-flop l2.

The flip-flop 12 is shown to be in a high current state during timing signal period t1. This relatively high current effectively closes gate 16 and consequently cuts olf the flow of clock pulses C from timing signal source 24 to the primary winding of transformer 28. As a result, gate 35 is now open, permitting output signal F1'C to appear on the output lead. Signal F lC is then fed back by way of lead 36 to the input f1 of stage F1. The negative pulse generated at the end of timing signal period t1, as a result of differentiating the pulse f1, causes stage F1 to switch to a state characterized by flip-flop 1,2 being in a low conducting state. Thus during timing signal period r2, gate 16 is open enabling a clock pulse C from timing signal source 24 to pass through to transformer 28. This effectively opens output gate 36 so that the clock pulse C is effectively sensed as an output signal FIC which is fed back by way of lead 87 onto input afl. The negative pulse generated at the end of timing signal period t2 as a result of differentiating the pulse f1 causes stage F1 to switch back to its original state characterized by flip-flop 12 being in a high conducting state.

The cycle of operation of stage F1 thus repeats as indicated by the waveforms for stage 1 shown in Fig. 5. Thus an output signal, scaled down by a factor of two from the clock signal frequency, is alternately available on outputs F l'C or F1C, respectively, of stage F1.

Consider now the operation of stage F2 which in combination with that of stage F1 effects an output pulse rate that scales down the clock pulse rate from timing signal source 24' by a factor of four. In this circuit, signals from timing signal source 24 are applied only to the gate 16" and the output signals FIC from stage F1 are applied by way of common lead 90 as inputs to gates 3S and 36" of stage F2. Thus the gate 16" has a steady rate sequence of clock pulses C applied thereto, while gates 35 and 36 each have a half-clock pulse rate input FlC applied as one of the inputs thereto. Flip-flop 12".is initially shown to be in alow current egsrassia conduction 'state andv gate 1`6'f fis" consequently open', caus- "ing 'a clock pulseC to be effectively sensed as output "F1E2C. This situation vis represented in the group of "waveforms for stage F2 of Fig. 5 during timing signal period t1. `This FlFZC pulse is fed back by way of lead "lw' state, at the end of timing signal period t3. The

i operational cycle rof stage F1 then repeats itself, as reference to the waveforms of Fig. 5 will reveal. Thus pulse "outputs representing the clock pulse frequency scaled -down by a factor of four are` alternately available from 'fvi'ous that additional stages, similar in circuitry tothe circuit shown in Fig. 6, can be used to scaledown the clock pulse rate still further, if so desired.

While the form of the invention shown and described herein is admirably adapted to fulfill theobjects primarily*v stated, `it is to be understood that it is not intended to confine the invention to the one form or embodiment disclosed herein, for itis susceptible of embodiment in vari- `ons otherforms.

What is claimed is:

l. A bistable state 4circuit arrangement comprising a transistor flip-flop circuit; a timing signal source; a pair of gating circuits,each having an input, an output, and a control lead, each said input lead responsive to signals from said timing `signal source; andalternating current coupled means including switching means responsive to said flip-flop circuit and signals from said timing signal source to generate oppositely phased signals onsaid conitrol `leads for controlling said gating circuits, whereby timing signals from said source are sensed on the output of one or the other of said gating circuits dependent on the state of said flip-flop circuit.

2. A signal gating circuit arrangement comprising a source of timing signalsg-a transistor flip-flop circuit; a pair of gating circuits for gating signals from said timing source; control means including direct current potential sources for normally operating one of said gating` circuits in an open condition and the other in a closed condition;

and a second transistor controlled by the state of saidy flip-flop circuit to gate signals from said timing source for energizing 'said control means to produce signals for reversing the operating conditions of said gating circuits.

3. A bistable state circuit arrangement comprising a source of timing signals; a single pathed transistor flipflop circuit capable of being triggered from one state to the other; an alternating current coupled driver circuit having a pair of outputs and a gated input responsive to timing signals from said source, said gated input .controlled by the state of said flip-flop circuit; a pair of output gates, each having an input, an output, and a control lead; and means conditioned by the outputs of sald driver circuit to provide oppositely phased signals on said control leads to thereby gate signals applied on said input leads from said timing source onto one or the other of said output leads.

4. A signal responsive transistor network comprising a timing signal source; a transistor nip-flop circuit having an output; a gating transistor having a base, an emrt ter, and a collector, the base thereof connected to the output of said flip-flop circuit, and the emitter thereof connected to said timing signal source; a transformer having a primary winding and a first and second .secondary winding, the collector of said gating transistor being connected to said primary winding; a rst gating circuit and a second gating circuit, each said gating circuit having one input thereto connected to a respective secenarywinding and i another `input thereto connected to said tirring signal source, and each gating Circuit having an outputlead, whereby signalsare generated oneither one yof said output leads dependent on the state of said 5. A signal responsive transistor network comprising a timing signalsource; a transistor flip-ilop circuithaving an output; agating transistor having `a base, an emitter, and a collector, the base thereof connected tothe output of said flip-flop circuit, andthe emitter thereof connected to said timing signal source; a transformer having `a` primary winding and a pair of oppositely wound secondary windings, the collector of said gating transistor being connected to said primary winding; a lirst gating circuit and a sec-ond gating circuit, each said gating circuit having one input thereto connected to a respective secondary winding and another input thereto connected -t`o said timing signal' source, and each said gating circuit having an output lead; and bias means connected to said secondary windings to control said gating circuits in accordance with the Vresponse of said transformer to signals from said timing signal source, whereby `signals are generated on either one of said output leads dependent on the state of said flip-nop circuit.

6. In combination, a double input transistor flip-flop circuit having an output lead; a timing signal source; a

\ transformer having a primary winding and a first and second secondary Winding; a gating transistor having a base, an` emitter, and a collector, Ythe base thereof connected to the output lead from said flip-flop circuit, the

-emitter thereof `connected to saidtiming signal source,

and the collector thereof connected to the primary windingof said transformer; a first gatecircuit and asecond gate circuit; an output lead from each secondary windingf connected to a respective one of said gatecircuits;

andan input to each said gate circuit fromsaid timing *signal source, whereby `upon `application `of a Ytrigger signal toone input of said flip-flop circuit, timing signals are gated out of one of said gate circuits, and upon the application ofa trigger signal to Vthe Vother input ofA said flip-dop circuit, timing signals are gated out of the other of said gate circuits.

7. A bistable state circuit arrangement comprising a first and second differentiating circuit; a transistor flip-flop circuit having a base, an emitter, and a collect-or, said lirst differentiating circuit providing input signals to the base of, and said second differentiating circuit providing input signals to the emtter of, said transistor hiphop; a source of square Wave signals; a gating transistor having a base, an emitter, and a collector, the base of said gating transistor connected to the collector Vof said flip-flop circuit and the emitter `of which is connected to said source; a transformer including a primary and two secondary windings, the collector output from said gating transistor being connected to the primary winding of said transformer; a pair of gating circuits, each of said gating circuits connected to the output of one of said secondary windings and each connected to said source; and an output lead from each said gating circuit, whereby signals from said source are sensed on either one of said output leads dependent on the application of a square wave signal on one or the other of said differentiating circuits.

8. A bistable state circuit arrangement comprising a first and second differentiating circuit; a transistor flipflop circuit having a base, an emitter, and a collector, said first differentiating circuit providing input signals to the base and said second differentiating circuit providing input signals to the emitter of said transistor ip-iiop; a source of square wave signals; a gating transistor having a base, an emitter, and a collector, the base of which is connected to the collector of said flip-flop circuit and the emitter of which is connected to said source; a transformer including a primary and two secondary windings, the collector of said gating transistor being connected to the primary winding of said transformer; a pair of gating circuits, each said gating circuits con- .nected to the output of one of said secondary windings and each said gating circuit connected to said source; control means for biasing the outputs of said secondary windings such that one said gating circuit is open in the absence of signals on said transformer from said source and the other gating circuit is open upon receipt of signals on said transformer from said source; and an output lead from each said gating circuit, whereby signals from said source are sensed on either one of said -output leads dependent on the application of a square wave signal on one or the other of said differentiating circuits.

9. A signal responsive network comprising a timing signal source; a flip-flop circuit; a transformer having a primary winding and a rst and second secondary winding; gating means controlled by the state of said flip-dop circuit to pass signals from said timing signal source onto the primary winding of said transformer; a tirst gating circuit and a second gating circuit, each said gating circuit having one input thereto connected to a respective secondary winding of said transformer and another input thereto connected to said timing signal source; an output lead associated with each said gating circuit; and direct current control means for biasing the respective outputs from said secondary windings such that one said gating circuit is open in the absence of signals being gated to the primary winding of said transformer from said timing signal source and the other said gating circuit is open when signals are gated to the primary winding of said transformer from said timing signal source, whereby signals are generated on either said output lead dependent upon the state of said Hip-flop circuit.

10. A signal responsive network comprising a timing signal source; a transformer having a primary winding and a first and second secondary winding; gating means to pass signals from said timing signal source onto the primary winding of said transformer; a rst gating circuit and a second gating circuit, each said gating circuit hav- -12 ing one. input thereto connected to a respective secondary winding of said transformer .and another input thereto connected to said timing signal source; an output lead associated witheach said gating circuit; and direct current control means for biasing the respective outputs from said secondary windings such that one said gating circuit t is open in the absence of signalsbeing gated to the primary winding of said transformer from said timing signal source and the other said gating circuit is open when signals are gated to the primary winding of said transformer from said timing signal source, whereby signals are generated on either said output lead.

l1. .A bistable transistor circuit arrangement comprising: a source of periodically recurring square wave signals varying between a high and low voltage level; .a transistor flip-flop having an output; a gating transistor having a base, an emitter, and a collector, the base thereof connected to the output of said tip-flop circuit and the emitter connected to said signal source; a transformer having a primary winding and first and second oppositely wound secondary windings, the collector of said gating transistor connected to said primary winding; a irst diode gating circuit and a second diode gating circuit, each said gating circuit having one input thereto connected to said signal source; a lirst diode clamping circuit including a source of high level voltage connecting said first secondary Winding to another input of said iirst gating circuit; a second diode clamping circuit including a source of low level voltage connecting said second secondary winding to another input of said second gating circuit; and an output lead for each said gating circuits.

References Cited in the tile of this patent UNITED STATES PATENTS 2,619,594r Goldberg Nov. 25, 1952 2,644,896 Lo July 7, 1953 2,698,382 Uglow et al Dec. 28, 1954 2,706,811 Steele a- Apr. 19, 1955 UNITED STATES PATENT OFFICEv CERTIFICATE 0F 4CORRECTION 1 t,Patent`NO'.2,S73,;384 i Eebrgaryioaigje Seymour Schoen et al.

It is hereby certified that error appears` in the printed Aspeclifficat'on of the above "numbered patent requiring correction and that the said Letters Patent should readas corrected below.

Column 4, line 48, for Hthe =22 volts" read the '22 volts f-; `,column '7, line 2l, for "appuearing" read `e` appearing wi; line 5'7, for "an output read on output ia; lcolumn 10, line' .2,- after "each" izmert Signed and sealed this 16th day of June' 1959.

(SEAL) Attest: 4

EARL E, AXLTNE t ROBERT o. 'WATSON Attesting Ocer Commissioner `of Patents 

